Mechanism and improvement of breakdown degradation induced by interface charge in UHV device

Author

Siddiqui, M.I. ; Prakash, Aravind ; Anwar, Muhammad Shoaib ; Gene Sheu ; Chen, P.A.

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Asia Univ., Taichung, Taiwan

fYear

2012

fDate

19-21 Sept. 2012

Firstpage

462

Lastpage

465

Abstract

This paper presents an innovative p-top engineering to simulate and optimize the breakdown degradations in different regions of the interdigitated layout such as source center(SC), drain center(DC), and flat region of an Ultra high voltage(UHV) device. In manufacturing of UHV device, breakdown voltage degradation takes place due to interface charges, current crowding and breakdown degradation was also observed at wafer-stage with temperature stress resulted from package level reliability tests. Optimizations are done to sustain high breakdown voltage by varying the p-top mask design to investigate the interface charge effect on breakdown. ESD test is also conducted to show the difference in interface charges after stress. A better stability has been obtained for maximum p-top length structure with respect to breakdown and ESD testing.

Keywords

electrostatic discharge; integrated circuit reliability; integrated circuit testing; interface phenomena; thermal stresses; ESD testing; breakdown voltage degradation; current crowding; drain center; electrostatic discharge; flat region; interdigitated layout; interface charge effect; p-top engineering; p-top mask design; package level reliability tests; source center; temperature stress; ultra high voltage device; wafer stage; Degradation; Electrostatic discharges; Impact ionization; Optimization; Stability analysis; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics (ICSE), 2012 10th IEEE International Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4673-2395-6

Electronic_ISBN

978-1-4673-2394-9

Type

conf

DOI

10.1109/SMElec.2012.6417186

Filename

6417186