A reconfigurable parallel inference processor for high speed fuzzy systems

An application specific parallel rule inference architecture is presented which is capable of performing an entire rule inference within one clock cycle. The architecture is composed of asynchronous self routing min and max blocks that are interlinked into a network as determined by the rules for the intended application. The inference processor does not have to fetch rules from memory because the rules are configured in the firmware structure; hence the inherent speed advantage. The design is targeted for high capacity Complex Programmable Logic Devices (CPLDs), whose ability to be reconfigured allows the application specific rule structure to be practical for real world systems