A power-scalable concurrent cascade 2-2-2 SC ΣΔ modulator for Software Defined Radio

This paper presents a flexible 1.2-V 90-nm CMOS cascade three-stage SC ΣΔ modulator with local resonation in the last two stages, unity signal transfer function and programmable (either 3 or 5 level) quantization in all stages. The chip reconfigures its loop filter order (2nd, 4th, 6th order), the clock frequency (from 40 to 240MHz) and scales the power consumption according to required specifications. These reconfiguration strategies are combined with the capability of concurrency in order to digitize up to three different wireless standards simultaneously. Experimental results demonstrate the flexibility of the proposed modulator, featuring a programmable noise shaping within a 100kHz-to-10MHz signal band, with adaptive power dissipation¹.