Title :
A study on the effect of test vector randomness on test length and its fault coverage
Author :
Sahari, M.S. ; A´ain, A.K. ; Grout, Ian
Author_Institution :
Dept. of Microelectron. & Comput. Eng., Univ. Teknol. Malaysia (UTM), Skudai, Malaysia
Abstract :
This paper presents a study on the impact of test sequence randomness and the fault coverage (FC) it could produce through the use of a modified structure of the conventional linear feedback shift register (LFSR). By using double input signals, the modified LFSR can control the number of test patterns generated and also prevents the sequences from being stuck in all zeroes state. Fault simulations on ISCAS´85 benchmark circuits show that a high FC for combinational logic circuits has been obtained. Another observation is that the modified structure could achieve high FC with a smaller test sequence compared to other reported test pattern generation (TPG) techniques.
Keywords :
automatic test pattern generation; combinational circuits; fault diagnosis; logic testing; shift registers; ISCAS´85 benchmark circuits; LFSR modified structure; TPG techniques; combinational logic circuits; double input signals; fault coverage; fault simulations; linear feedback shift register; test length; test pattern generation techniques; test sequence; test vector randomness effect; Benchmark testing; Central Processing Unit; Circuit faults; Computers; TV; Vectors;
Conference_Titel :
Semiconductor Electronics (ICSE), 2012 10th IEEE International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4673-2395-6
Electronic_ISBN :
978-1-4673-2394-9
DOI :
10.1109/SMElec.2012.6417196
