Technology-based architectural analysis of operand bypass networks for efficient operand transport

As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift micro-architectural design focus from operation computation to operand transport. Operand bypass networks of out-of-order superscalar processors are particularly demanding of wiring resources. Forwarding path delay has become a limiting factor of processor performance. This paper proposes a novel technology-based methodology to evaluate bypass network configurations by predicting operand transport cost. It combines technology modeling techniques with cycle-accurate simulation of benchmark applications to characterize operand movement and storage requirements. Our analysis shows that the operand transport cost heavily depends on the physical location of functional units (FUs) and instruction steering strategy. We propose a traffic-based placement which places FUs based on the transport distribution pattern; and a geometry-driven instruction steering which tries to assign each pair of dependent instructions to adjacent computing resources. Performance is evaluated on an aggressive eight-way, 16 functional unit processor operating at 1.9 GHz in 100 nm technology. Combining these two techniques, the IPC penalties resulting from wire delay latency can be kept within 6.8% of the ideal zero bypass delay processor for Spec2000Int and within 5.5% for MediaBench.