A many-core platform implemented for multi-channel seizure detection

This paper presents a reconfigurable many-core platform performing fixed point DSP applications supporting up to 64 cores routed in a hierarchical network. To demonstrate an application, electroencephalogram (EEG) seizure detection and analysis is mapped onto the cores. The individual cores are based on a 5 stage RISC pipeline architecture optimized to support communication to other cores on the platform. To reconfigure the platform, programs are loaded onto each of the cores. Communication between cores is implemented using low-area routers that partitions computational cores into hierarchical clusters resulting in a low network diameter. The routers use a packet-switched protocol that minimizes circuitry which further reduces circuit size in comparison to the computational circuitry. A globally asynchronous, locally synchronous (GALS) architecture is implemented to eliminate global clock routing which consumes high levels of power due to long propagation and thus high capacitive loading from many cores. Additionally, cores not configured for an application has its local clock disabled which turns off unused cores. The overall result is a platform with lower power consumption than a traditional single core DSP with the reconfigurability lacking in an ASIC. Applications tested within the mapping include the Fast Fourier Transform (FFT) and Finite Impulse Response (FIR) filter. The seizure detection and analysis algorithm, when mapped onto the many-core platform, takes 5663 cycles to execute in 14.45 μs. The prototype SoC is implemented in 65 nm CMOS which contains 64 cores and occupies 8.41 mm².