DocumentCode
302627
Title
Analysis of power consumption in a simple embedded data path unit
Author
Rahkonen, Timo
Author_Institution
Electron. Lab., Oulu Univ., Finland
Volume
2
fYear
1996
fDate
12-15 May 1996
Firstpage
552
Abstract
An experimental 8 bit data path consisting of an ALU and 4-register register file is implemented in a 1.2 μm CMOS process. The data path features AND and OR operations that are implemented as wired-or functions on precharged buses, making simultaneous masking and addition operations possible without extra hardware. Maximum operating frequency is 25 MHz, area 600 μm×610 μm (0.37 mm2) and equivalent power dissipating capacitor of clocking and data buses is about 30 pF which corresponds to 30 pF/1700 transistors=18 fF per transistor using a 5 V supply
Keywords
CMOS logic circuits; digital arithmetic; real-time systems; 1.2 micron; 25 MHz; 5 V; 8 bit; ALU; AND operations; CMOS process; OR operations; embedded data path unit; power consumption analysis; precharged buses; register file; CMOS process; Clocks; Data buses; Demodulation; Energy consumption; Frequency; Laboratories; Power capacitors; Testing; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541784
Filename
541784
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