A scalable VLSI architecture for high resolution real time object detection

Author

Wosnitza, M. ; Cavadini, M. ; Thaler, M. ; Tröster, G.

Author_Institution

Electron. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland

Volume

2

fYear

1996

fDate

12-15 May 1996

Firstpage

644

Abstract

This paper describes a VLSI-based multiprocessor system for object detection, targeting high resolution images. A set of basic correlation algorithms as well as a moment based rotation invariant algorithm are presented and an architecture for VLSI implementation is proposed. The architecture consists of multiple identical processing elements working in SIMD (Single Instruction Multiple Data) mode. Each processing element is capable of processing a set of different algorithms, thus covering a wide field of applications. A system consisting of 8 processing elements realized in 0.6 μm CMOS technology is able to localize a 128×128 pixel template in a 1024×1024 pixel image at a rate of 10 frames/second

Keywords

CMOS digital integrated circuits; VLSI; correlation methods; digital signal processing chips; image resolution; object detection; parallel architectures; real-time systems; 0.6 micron; CMOS technology; SIMD mode; correlation algorithms; high resolution images; high resolution object detection; moment based rotation invariant algorithm; multiprocessor system; real time object detection; scalable VLSI architecture; Costs; Image processing; Intelligent robots; Laboratories; Machine vision; Object detection; Pixel; Real time systems; Robot vision systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541807

Filename

541807