A new hardware efficient, low power FIR digital filter implementation approach

This paper presents a new hardware efficient approach for low power implementation of FIR digital filters. To reduce power consumption, filter´s multipliers are split to global and local multiplication units by splitting CSD representation of filter coefficients (SCSD). This idea not only reduces the number of required adders for multipliers implementation, but also decreases logic depth in multiplier logic paths. For 8-bit coefficients, it achieves a hardware average saving improvement of 49% over CSD and 42% over DM representations. It was found that an average saving improvement of 39% over CSD and 18% over DM representations is achievable in 16-bit coefficients.