VLSI implementation of a complete chip set for an MPEG2 real-time encoder

Author

Kobayash, T. ; Saito, Ryo ; Kimura, Junki ; Nakatomi, T. ; Nagai, N. ; Arai, Hiroyuki ; Wuertele, D. ; Fujiwara, H. ; Nishi, Kentaro ; Okada, Yutaka

Author_Institution

Graphics Commun. Labs., Japan

Volume

2

fYear

1996

fDate

12-15 May 1996

Firstpage

660

Abstract

We have developed a real-time encoder chipset which completely complies to the standard ISO/IEC13818-2|ITU-TH.262 (also known as “MPEG2 Video”), for the Main Profile at Main/High Level. This set consists of the following five chips: the “PRE” (Pre-processing) chip, the “CME” (Coarse Motion Estimation) chip, the “COD” (Predictive Coding) chip, the “QVL” (Orthogonal Transformation, Quantization, and Variable Length Coding) chip, and the “FME” (Fine Motion Estimation) chip. One set of these five chips is sufficient for real-time encoding of source images equivalent to the ITU-RBT.601 standard, and by connecting eight sets together, HDTV level real-time encoding is possible

Keywords

VLSI; data compression; digital signal processing chips; high definition television; linear predictive coding; motion estimation; quantisation (signal); real-time systems; telecommunication computing; video coding; HDTV level encoding; ISO/IEC13818-2; ITU-RBT.601; ITU-TH.262; MPEG2 real-time encoder; QVL; VLSI implementation; chip set; coarse motion estimation chip; fine motion estimation chip; orthogonal transformation; predictive coding chip; preprocessing chip; quantization; standard; variable length coding; Encoding; ISO standards; Image coding; Image converters; Motion estimation; Predictive coding; Quantization; Signal processing algorithms; Streaming media; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541811

Filename

541811