Architecture for MPEG2 MP@HL real time motion estimator

Author

Onoye, Takao ; Fujita, Gen ; Shirakawa, Isao ; Matsumura, Kenji ; Ariyoshi, H. ; Tsukiyama, Shuji

Author_Institution

Dept. of Inf. Syst. Sci., Osaka Univ., Japan

Volume

2

fYear

1996

fDate

12-15 May 1996

Firstpage

664

Abstract

A VLSI architecture of a motion estimator is proposed, dedicated to MPEG2 MP@HL, which adopts a two-level hierarchical searching algorithm in detecting motion vectors. A novel mechanism is introduced into the full-search procedure which attempts the maximum possible reuse of reference pixels to reduce the bandwidth of frame memory interface. The proposed architecture has been integrated into a 0.6 μm triple-metal CMOS chip which contains 1200 K transistors on a 12.2×12.7 mm² die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL

Keywords

CMOS digital integrated circuits; VLSI; data compression; digital signal processing chips; motion estimation; real-time systems; telecommunication computing; video coding; 0.6 micron; 133 MHz; MPEG2 MP@HL; VLSI architecture; frame memory interface; full-search procedure; real time motion estimator; triple-metal CMOS chip; two-level hierarchical searching algorithm; Asynchronous transfer mode; Digital video broadcasting; Encoding; Image storage; Motion detection; Motion estimation; Multimedia communication; Satellite broadcasting; TV broadcasting; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541812

Filename

541812