DocumentCode
302654
Title
Finite wordlength effects analysis and wordlength optimization of a multiplier-adder based 8×8 2D-IDCT architecture
Author
Kim, Seehyun ; Sung, Wonyong
Author_Institution
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
Volume
2
fYear
1996
fDate
12-15 May 1996
Firstpage
672
Abstract
The finite wordlength effects of a multiplier-adder based 8×8 2D-IDCT (inverse discrete cosine transform) are analytically modeled. Based on the error model, the set of optimum wordlengths conforming to the IEEE specifications is determined. There is a close agreement between the model and the bit-accurate simulation results
Keywords
IEEE standards; adders; computer architecture; digital arithmetic; digital signal processing chips; discrete cosine transforms; error analysis; image processing; multiplying circuits; 2D IDCT architecture; IEEE specifications; discrete cosine transform; error model; finite wordlength effects analysis; inverse DCT; multiplier-adder architecture; optimum wordlengths; wordlength optimization; Computer architecture; Decoding; Discrete cosine transforms; Discrete transforms; Finite wordlength effects; Fixed-point arithmetic; Matrix decomposition; Quantization; Telephony; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541814
Filename
541814
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