A high-speed magnitude comparator with small transistor count

Author

Cheng, Shun-Wen

Author_Institution

Tamkang Univ., Taipei, Taiwan

Volume

3

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

1168

Abstract

The comparator is a very basic and useful arithmetic component of digital systems. An individual, compact, high-performance, good cost-benefit ratio comparator core plays an important role on almost all hardware sorters. The study proposes a fine cost-performance ratio comparator design. Based on modified 1´s complement principle and conditional sum adder scheme, the proposed design has small transistor count and short propagation delay. Post-layout simulations based on TSMC 0.6μm 1P3M CMOS process has completed. It shown a 64-b static CMOS comparator of the proposed architecture only needs 1,556 transistors and 4.2ns.

Keywords

CMOS logic circuits; VLSI; adders; combinational circuits; comparators (circuits); high-speed integrated circuits; integrated circuit design; logic CAD; sorting; CMOS process; VLSI; carry out bit information; conditional sum adder scheme; digital IC; digital comparator; good cost-performance ratio design; high-performance comparator core; high-speed magnitude comparator; inverters; post-layout simulations; short propagation; small transistor count; sorting networks; two-input AND gates; two-input OR gates; Adders; CMOS integrated circuits; CMOS logic circuits; CMOS process; Computer architecture; Digital arithmetic; Digital systems; Hardware; Propagation delay; Sorting;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301720

Filename

1301720