DocumentCode :
302668
Title :
An improved architecture for the adaptive discrete cosine transform
Author :
Martin, Frunçois ; Bull, David R.
Author_Institution :
Centre for Commun. Res., Bristol Univ., UK
Volume :
2
fYear :
1996
fDate :
12-15 May 1996
Firstpage :
742
Abstract :
This paper presents a new approach to the efficient realisation of the discrete cosine transform for the specific case of interlaced image sequence coding. In such cases, the conventional approach of decomposing each frame or frame difference into 8×8 blocks is often no longer satisfactory and an adaptive architecture capable of processing either 8×8 or two 4×8 blocks is desirable. The approach described is based on the decomposition used by Madisetti, modified to maximise shared hardware resources and to exploit arithmetic redundancy using primitive operator methods. The resulting architecture is compared with alternative implementation options using an area-time metric with savings in excess of 50% having been observed
Keywords :
adaptive signal processing; discrete cosine transforms; image coding; image sequences; redundancy; adaptive discrete cosine transform; area-time metric; arithmetic redundancy; decomposition; interlaced image sequence coding; primitive operator methods; shared hardware resources; Arithmetic; Buildings; Discrete cosine transforms; Equations; Hardware; Image coding; Image communication; Image sequences; Signal processing algorithms; Sparse matrices;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
Type :
conf
DOI :
10.1109/ISCAS.1996.541832
Filename :
541832
Link To Document :
بازگشت