Novel systolic array design for discrete cosine transform with high throughput rate

In this paper, a new approach for the realization of 1D discrete cosine transform (1D-DCT) is presented. This approach is based on a new formulation of an odd prime-length DCT which uses two half-length cyclic convolutions with the same form which can be computed in parallel. Using this approach, a new efficient systolic array with outstanding performance in structural regularity, hardware cost of the PE´s, average computation time, and I/O cost has been obtained, which is well suited for VLSI realization. The average computation time has been reduced to one half and the throughput has been doubled, as compared with a previous design. It possesses also a much lower control complexity, a simpler interconnection structure, and a simpler hardware structure of the PE´s, having thus a shorter cycle time. Moreover, it owns all other outstanding features of the systolic array previously proposed