Title :
A novel VLSI architecture for the full search block matching algorithm using systolic array
Author :
Pan, Sung Bum ; Chae, Seung Soo ; Park, Rae-Hong
Author_Institution :
Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea
Abstract :
This paper presents a new VLSI architecture of the full search block matching algorithm (FSBMA) using systolic array for motion estimation of moving sequences. The proposed hardware architecture is faster than the conventional ones with lower hardware complexity. It is modeled in very high speed integration circuit hardware description language (VHDL) and simulated to show its functional validity
Keywords :
VLSI; hardware description languages; image matching; motion estimation; systolic arrays; VHDL simulation; VLSI architecture; full search block matching algorithm; hardware complexity; motion estimation; moving sequence; systolic array; Circuit simulation; Hardware; Motion estimation; Signal processing; Signal processing algorithms; Systolic arrays; Utility programs; Very large scale integration; Video compression; Video signal processing;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541834
