Design of robustly testable static CMOS parity trees derived from binary decision diagrams

A robustly testable design of static CMOS parity trees is presented. A test set for such a tree which cannot be invalidated in the presence of arbitrary timing skews and/or circuit delays can be derived. The constituents of the parity tree are static CMOS EXCLUSIVE-OR (EX-OR) gates, which are constructed from their corresponding binary decision diagrams (BDDs). The EX-OR gates in the tree can have any number of inputs. The robust test set detects all the single stuck-open, stuck-on, and stuck-at faults when both logic and current monitoring are done. It is shown that such implementations of parity trees are testable with a test set of size O(log_kn), where n is the number of primary inputs and k is a circuit parameter