Title :
Activity measures for fast relative power estimation directed numerical transformation for low power DSP synthesis
Author :
Nguyen, Huy ; Chatterjee, Abhijit
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
In this paper, we propose a method for optimizing digital signal processing (DSP) systems for both power and circuit area. The optimization involves application of numerical transformations to the matrices of a linear system. A greedy search algorithm is used, along with fast and efficient activity estimator to synthesize low power systems. The method is applicable to bit-serial, nibble-serial as well as fully word-parallel architectures. In this paper we focus primarily on bit-serial architectures and show that up to 35 percent savings in power and hardware may be obtained
Keywords :
CMOS digital integrated circuits; adders; circuit optimisation; digital signal processing chips; discrete event simulation; integrated circuit design; integrated circuit modelling; multiplying circuits; activity measures; bit-serial architectures; circuit area; digital signal processing; fully word-parallel architectures; greedy search algorithm; linear system; low power DSP synthesis; nibble-serial architectures; numerical transformations; relative power estimation; Adders; Capacitance; Circuit synthesis; Digital signal processing; Hardware; Linear systems; Optimization methods; Power measurement; Signal synthesis; Voltage;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541890
