Title :
Design of signature registers for double error bit identification
Author :
Damarla, T. Raju ; Stroud, Charles E.
Author_Institution :
U.S. Army Res. Lab., Nat. Res. Council, Fort Monmouth, NJ, USA
Abstract :
Design techniques for Signature Analysis Registers (SARs) and Multiple Input Signature Registers (MISRs) are presented along with algorithms which facilitate the identification of all single and double errors in faulty circuit output responses. The hardware area overhead associated with this approach is less than that of previous error bit identification techniques. The applications for which this technique is best suited include Built-In Self-Test (BIST) with fault diagnosis capabilities for memories and other regular structures
Keywords :
built-in self test; error analysis; error detection; fault diagnosis; identification; logic design; logic testing; BIST; double error bit identification; fault diagnosis capabilities; faulty circuit output responses; hardware area overhead; memories; multiple input signature registers; signature analysis registers; signature register design; Algorithm design and analysis; Built-in self-test; Circuit faults; Circuit testing; Error correction; Fault diagnosis; Polynomials; Random access memory; Read only memory; Registers;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541902
