Synchronous implementation of a counterflow pipeline processor

The counterflow pipeline principle was originated by Sproull (1994) as an architecture for asynchronous processor design. As such, it offers many useful properties including local control, local message passing, and an overall simple design methodology. We have taken these same ideas and used them in the design of a synchronous processor. Since the speed of today´s processors is being limited more and more by the global signal routing, an architecture which seeks to limit these may indeed result in a significant speed increase. We intend to show that the local interchange of information and simple design can allow for longer pipelines and increased processor throughput