• DocumentCode
    302694
  • Title

    A novel video signal processor with reconfigurable pipelined architecture

  • Author

    Yeong-Kang Lai ; Chen, Ldang-Gee ; Ming-Cheng Chiang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    4
  • fYear
    1996
  • fDate
    12-15 May 1996
  • Firstpage
    73
  • Abstract
    A programmable 133 MOPS (mega operations per second) processor is designed for video signal processing. It consists of Data-path Processing Part (DPP) and Address Generating Part (AGP). Through a flexible network, the DPP can be efficiently reconfigured as any types of pipelined architecture in terms of video coding algorithms. It is especially suitable to implement irregular algorithms, such as the fast discrete cosine transform (FDCT) and the three-step hierarchical search (3SHS) algorithm for motion estimation. The AGP can generate addresses to perform desired memory access operations for various irregular video coding algorithms. By using this video signal processor (VSP), video processing systems can be easily implemented, and video data can also be smoothly processed in single or multiple VSP configurations. The realization of MPEG-2 is evaluated, and its performance is also presented
  • Keywords
    CMOS digital integrated circuits; VLSI; data compression; digital signal processing chips; discrete cosine transforms; motion estimation; pipeline processing; reconfigurable architectures; video coding; video signal processing; 3SHS algorithm; CMOS VLSI chip; DSP chip; MPEG-2; address generating part; fast DCT; fast discrete cosine transform; flexible network; irregular algorithms; memory access operations; motion estimation; programmable processor; reconfigurable pipelined architecture; three-step hierarchical search algorithm; video coding algorithms; video signal processor; Arithmetic; Computer architecture; Decoding; Discrete cosine transforms; Motion estimation; Process design; Signal processing; Signal processing algorithms; Very large scale integration; Video coding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
  • Conference_Location
    Atlanta, GA
  • Print_ISBN
    0-7803-3073-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1996.541904
  • Filename
    541904