ADC performance limitations due to quantizer non-idealities

Author

Kothapalli, Ganesh

Author_Institution

Edith Cowan Univ., Perth, WA, Australia

Volume

3

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

1240

Abstract

A low-voltage low-power CMOS Sigma-Delta Modulator (SDM) is presented. The influence of a dynamic latched comparator on the performance of the SDM are studied with the help of SPICE simulations. SPICE BSIM4 models are used to study the transient behaviour of the overall circuit. The latched comparator is devised to be used to detect very small differential signals in the presence of large common-mode signals. An 8-bit second-order Sigma-Delta Modulator is used to demonstrate the limitations and potential, solutions associated with the use of the latched comparator. The aim of this study is to use such an ADC in the CMOS imagers to be realized in a low-cost standard digital process technology. Another aim of this study is to utilize an identical design layout of the latched comparator to quantize the full-scale range of signals (LSB to MSB).

Keywords

CMOS integrated circuits; SPICE; comparators (circuits); error compensation; low-power electronics; quantisation (signal); sigma-delta modulation; ADC performance limitations; CMOS imagers; CMOS sigma-delta modulator; SPICE simulations; dynamic latched comparator; error compensation; large common-mode signals; low-voltage low-power modulator; quantizer nonidealities; second-order modulator; small differential signals; transient behaviour; CMOS process; Circuit simulation; Delta-sigma modulation; Feedback; Latches; MOSFETs; Parasitic capacitance; SPICE; Semiconductor device modeling; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301738

Filename

1301738