Delay-testable non-scan sequential circuits with clock suppression

We present a method of designing non-scan sequential circuits in which every path can be tested either by a robust test or a validatable non-robust (VNR) test. It uses a novel clock suppression scheme which does not require any suppression pattern generation circuitry. It is shown that complete delay testability can be achieved with a little extra cost in inputs and latches, using a constant-weight encoding. A comparison of area-optimized two-level implementations and our delay-testable implementations of some of the MCNC synthesis benchmarks, in terms of number of product terms and latch-latch paths in the next-state logic, is presented