A practical hardware design for the keypoint detection in the SIFT algorithm with a reduced memory requirement

SIFT (Scale Invariant Feature Transform) generates image features widely used to match objects in different images. Previous work on hardware-based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement the keypoint detection in SIFT with a less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. The processing order of the vertical filtering ahead of the horizontal operation also reduces the storage space. The computational complexity is reduced by sharing the Gaussian filter bank for multiple octaves. As a result, the memory size is reduced by more than 80 percent without a complexity increase in hardware design.