Unbalanced current latch sense amplifier for low-power high-speed PLDs

This paper describes an unbalanced current latch sense amplifier (UCLSA) for low-power high-speed programmable logic device (PLD) design. With one side of the differential inputs of the UCLSA connected to the bit line and the other to a fixed bias, the UCLSA amplifies the small voltage difference generated in the single-ended bit line of the PLD. A pair of differential signals are generated and the sense current is stopped automatically. The UCLSA can amplify an input voltage swing on the bit line as small as 20 mV. Low-power and high-speed performances can be achieved by using the UCLSA