Title :
A low-power state-sequential Viterbi decoder for CDMA digital cellular applications
Author :
Kang, Inyup ; Willson, Alan N., Jr.
Author_Institution :
Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
Abstract :
An efficient state-sequential VLSI architecture and low-power design methodologies, ranging from system-level to layout-level, are presented to implement a low-power state-sequential R=1/2, K=9 Viterbi decoder for CDMA digital cellular applications
Keywords :
CMOS digital integrated circuits; VLSI; Viterbi decoding; cellular radio; code division multiple access; digital radio; digital signal processing chips; telecommunication computing; CDMA digital cellular applications; low-power design; state-sequential VLSI architecture; state-sequential Viterbi decoder; AWGN; Bit error rate; Convolutional codes; Degradation; Maximum likelihood decoding; Multiaccess communication; Noise measurement; Quantization; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541954
