Logic synthesis with the CDPD circuit technique

Author

Pihl, J. ; Aas, E.J.

Author_Institution

Fac. of Electr. & Comput. Eng., Norwegian Univ. of Sci. & Technol., Trondheim, Norway

Volume

4

fYear

1996

fDate

12-15 May 1996

Firstpage

288

Abstract

A system for automated logic synthesis with a modified form of the clock-and-data precharged dynamic (CDPD) circuit technique is presented. The system synthesizes fast one clock cycle modules of unate Boolean functions in short design time. A novel true single phase clocking (TSPC) flip-flop suitable for CDPD synthesis simplifies interfacing with standard edge triggered clocking schemes. An 8-bit adder structure suitable for CDPD implementation was synthesized with the CDPD synthesis system and fabricated in a 0.8 μ standard CMOS process. The adder was functional at a clock frequency of more than 250 MHz

Keywords

Boolean functions; CMOS logic circuits; adders; clocks; flip-flops; logic CAD; logic design; 0.8 micron; 250 MHz; 8 bit; CDPD circuit; CMOS process; adder; automated logic synthesis; clock-and-data precharged dynamic circuit; edge triggered clocking; true single phase clocking flip-flop; unate Boolean function; Adders; Boolean functions; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Combinational circuits; Logic circuits; Physics computing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541958

Filename

541958