Feedback-controlled split-path CMOS buffer

New CMOS buffers, called feedback-controlled split-path (FS) CMOS buffers, are proposed and analyzed. By using the control of the output feedback signal, the short-circuit current of the output stage can be eliminated. The pull-high and pull-down driving paths of the output stage are split and they can be sized individually to acquire lower delay time, smaller area, and lower power dissipation. A general method is also proposed to further eliminate the short-circuit current in each stage of the FS buffer and to reduce the area, power dissipation, and delay time. High-speed buffers operated at 200 MHz are designed with 0.5ns rise/fall time and 2.5 nF output load. Simulation results show that the power-delay product of the FS buffers with two split-paths and four split-paths are only 59% and 47% that of the conventional fixed-taper buffer, respectively