A cost-effective VLSI architecture for high-throughput sequential decoder

This paper presents a new VLSI solution for high-speed digital communications based on long-constraint convolutional codes. The proposed VLSI architecture implements a modified sorter-based sequential decoding algorithm with an achievable maximum decoding rate of 25 Mbits/s. Unlike its previous version based on shiftable content addressable memory (SCAM) only, path recording is now implemented on an embedded SRAM module whose size is determined by path depth (d) and survived nodes (S). That is, both SCAM and SRAM are exploited to implement the sorter kernel. Results show that, for a (2,1,7) code, both power consumption and silicon area can be improved by 50% on the average, making the new proposal very suitable for high-speed convolutional code applications