A neural network algorithm for hardware-software verification

Author

Rebaiaia, Muhamed Larbi ; Jaam, Jihad Mohammad ; Hasnah, Ahmad Mojahid

Author_Institution

Comput. Sci. Dept., Univ. of Batna, Algeria

Volume

3

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

1332

Abstract

Formal verification is the task of proving that a property holds for a model of a design. This paper examines the idea of a Neural Network-based algorithm used to find the set of states that makes a specification valid. The paper addresses a singular approach for those doing theoretical research for the verification of soft programs, and, for hardware designers. The approach of the application of the Artificial Neural Network is not new, but it becomes interesting if one can improve the truth-building efficiency by using some known artifices. Topics described include Integer Linear Programming, Propositional Logic, Model Checking, Satisfiability problems (SAT) and Artificial Neural Networks (ANN).

Keywords

Boolean functions; computability; formal verification; hardware-software codesign; integer programming; linear programming; neural nets; Boolean formula; EDA design; formal verification; hardware-software verification; integer linear programming; model checking; neural network algorithm; propositional logic; satisfiability problems; specification validity; truth building efficiency; Algebra; Artificial neural networks; Circuits; Computer science; Formal verification; Logic programming; Logic testing; Neural network hardware; Neural networks; Software algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301761

Filename

1301761