A parallel image processor chip for real-time applications

This paper describes the design and implementation of a general purpose parallel image processor chip called the Sliding Memory Plane (SliM) Image Processor. The chip consists of mesh-connected 5×5 processing elements (PEs), operates at 25 MHz and gives 625 MIPS. Due to the idea of sliding, that is, overlapping the inter-PE communication with the computation, the SliM chip can greatly reduce the inter-PE communication overhead, a disadvantage of existing array processors. Because of a mesh topology, the chip itself has native scalability, and therefore, a large number of chips can be easily connected to form an array processor for real-timing signal and image processing applications