Low Power Instruction Cache with Word Selective Line Buffer

In this paper, we propose Word Selective Line Buffer (WSLB) which takes advantages from the line buffer and sub-banking cache. Our proposed WSLB cache includes two significant features that are Address Latch Register (ALR) and Variable Length Sub-Banking (VLSB). ALR can make reduction of energy dissipation by eliminating access TLB while the line buffer and sub-banking technique can combined by VLSB. These two features can make achieve cache dynamic power reduction by a 58.2% and Energy-Delay (ED) product reduction by 57.2% of baseline cache without performance degradation. In case of comparing with the conventional line buffer, the ED product is improved by average 12%. In addition, we evaluate this trend is maintained even if the cache configurations that are cache capacity and associativity changes.