Process Variations and Noise Analysis on a Miller Capacitance Tuned 1.8_2.4-GHz Dual-Band Low Noise Amplifier

Author

Balemarthy, Deepak ; Paily, Roy

Author_Institution

ECE Dept, Indian Inst. of Technol. Guwahati, Guwahati, India

fYear

2009

fDate

28-29 Dec. 2009

Firstpage

414

Lastpage

418

Abstract

This paper discusses design of inductively source degenerated dual-band low noise amplifiers (LNA) in a standard CMOS 0.18 Â¿m process. The dual-band LNA can be tuned to either 1.8-GHz or 2.4-GHz. The LNA is implemented both by Miller capacitance tuning and by capacitor selection using switches. In both the designs, the parasitic effects of bond wire, bond pads and ESD protection circuits are considered. Effect of process variations on LNA performance and noise analysis of LNA are also discussed.

Keywords

CMOS integrated circuits; UHF amplifiers; capacitors; electrostatic discharge; low noise amplifiers; switches; tuning; ESD protection circuits; Miller capacitance; bond pads; bond wire; capacitor selection; dual-band low noise amplifier; frequency 1.8 GHz; frequency 2.4 GHz; noise analysis; parasitic effects; process variations; size 0.18 mum; standard CMOS process; switches; tuning; Bonding; CMOS process; Capacitors; Circuit optimization; Dual band; Electrostatic discharge; Low-noise amplifiers; Parasitic capacitance; Switches; Wire; Low-noise amplifier (LNA); dual-band LNA; gain; impedance matching; inductively source degenerated LNA; noise analysis; noise figure; process variations;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT '09. International Conference on

Conference_Location

Trivandrum, Kerala

Print_ISBN

978-1-4244-5321-4

Electronic_ISBN

978-0-7695-3915-7

Type

conf

DOI

10.1109/ACT.2009.108

Filename

5376601