Dynamic assembling application to signal processing to generate time efficient sum of multiplications

In this paper, the application of dynamic assembling to the generation, on a sequential type processor of the basic time efficient instructions set required to perform any sum of multiplications, is presented. The considered procedure is based on the use of elementary machine instructions (such as add or subtract register, shift register) applied to integer coefficients represented in their minimal canonical signed-digit form. Examples of dynamic assembling application either at assembling time or at execution time, as well as results, are discussed. It is shown that improvement [expressed in terms of machine cycles reduction] can be as large as 20 providing thus an effective multiplication rate of the order of 1 to 2 million per second on a processor with an instruction cycle of 100 ns.