Title :
A Parallel-Serial Decimal Multiplier Architecture
Author :
Dadda, L. ; Pisoni, M. ; Santambrogio, Marco D.
Abstract :
Derived from a parallel multiplier, a parallel-serial decimal multiplier is proposed in which the multiplicand is assumed in parallel whereas the multiplier is in digit-serial form. A scheme for a parallel-serial decimal multiplier is presented, using BCD digits. The multiplicand is assumed in parallel, the multiplier in digit-serial form. The values of the Digit Products in the successive columns of the product array are added in binary and converted in decimal. Their decimal alignment generates a set of three or four serial decimal numbers whose sum is the product. The parallel-serial proposal substantially reduces complexity and it exploits overlapping update to speed up the pipeline. Evaluation on a basic implementation on FPGAs is compared against another embedded multiplier approach, showing that the proposed scheme achieves an increasing advantage as the input size increases.
Keywords :
binary codes; field programmable gate arrays; multiplying circuits; pipeline processing; BCD digits; FPGA; complexity reduction; decimal alignment; digit product values; digit-serial form; embedded multiplier; parallel multiplicand; parallel-serial decimal multiplier architecture; pipeline; product array; serial decimal numbers; Adders; Arrays; Clocks; Delay; Field programmable gate arrays; Registers; Decimal Multiplier; FPGA; Multiplier;
Conference_Titel :
Computational Science and Engineering (CSE), 2012 IEEE 15th International Conference on
Conference_Location :
Nicosia
Print_ISBN :
978-1-4673-5165-2
Electronic_ISBN :
978-0-7695-4914-9
DOI :
10.1109/ICCSE.2012.50
