DocumentCode
3028242
Title
Hardware implementation of FIR filter
Author
Hu, Xiao-li ; Wang, Feng-ying ; Zhang, Min
Author_Institution
Sch. of Inf. Eng., Inner Mongolia Univ. of Sci. & Technol., Baotou, China
fYear
2011
fDate
26-28 July 2011
Firstpage
341
Lastpage
343
Abstract
This paper is based on the basic theory of FIR digital filters,It completed the FIR filter design based on programmable logic device-FPGA, hierarchical design, modular design is used in the paper, a distributed algorithm filter hardware design and its use QuartusII simulation software.
Keywords
FIR filters; digital simulation; distributed algorithms; field programmable gate arrays; FIR digital filter design; FPGA; QuartusII simulation software; distributed algorithm filter hardware design; hardware implementation; hierarchical design; modular design; programmable logic device; Digital signal processing; Field programmable gate arrays; Filtering algorithms; Finite impulse response filter; Hardware; Table lookup; Distributed algorithm; FIR filter; FPGA; VHDL language;
fLanguage
English
Publisher
ieee
Conference_Titel
Multimedia Technology (ICMT), 2011 International Conference on
Conference_Location
Hangzhou
Print_ISBN
978-1-61284-771-9
Type
conf
DOI
10.1109/ICMT.2011.6001961
Filename
6001961
Link To Document