Compacting randomly generated test sets

A technique using genetic algorithms is presented for the generation of compact test sets for combinational VLSI circuits. The technique combines a previously proven method for random test pattern generation with adaptive searching capabilities to produce high-quality test sets. A series of experiments demonstrated that the technique performed consistently better than the traditional method. On average, the method is able to produce test sets that are approximately 20% smaller than the starting configuration. To place this in perspective, its solutions are on average 13% more compact than those produced by a traditional method with no loss in fault coverage