Title :
Parallel calculation of 3-D parasitic resistance and capacitance with linear boundary elements
Author :
Zhou, Wenming ; Wang, Zeyi ; Rao, Lm
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
Because of the widespread application of deep sub-micron and multilayer routing techniques, the interconnection parasitic influence has more and more effect on the performance of VLSI circuits. Parallel direct boundary element calculation of three-dimensional (3-D) resistance and capacitance is an important method for fast extraction. In this paper, a parallel algorithm to implement linear boundary element calculation using PVM (Parallel Virtual Machine, distributed calculating software) is introduced. The hierarchical calculation scheme of the setup and solution processes of linear equations is discussed. At the end, the performance and workload balance of the algorithm are analyzed
Keywords :
VLSI; boundary-elements methods; capacitance; circuit CAD; linear algebra; mathematics computing; network routing; parallel algorithms; resource allocation; 3D parasitic resistance; PC network; PVM; Parallel Virtual Machine; VLSI circuit performance; capacitance; hierarchical calculation scheme; linear boundary elements; linear equations; multilayer routing techniques; parallel algorithm; parallel calculation; parallel direct boundary element calculation; performance; sub-micron techniques; three-dimensional resistance; workload balancing; Algorithm design and analysis; Equations; Integrated circuit interconnections; Nonhomogeneous media; Parallel algorithms; Parasitic capacitance; Performance analysis; Routing; Very large scale integration; Virtual machining;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
DOI :
10.1109/ASPDAC.1997.600200
