A high-throughput modular architecture for three-step search block matching motion estimation

The three-step hierarchical search block matching motion estimation algorithm has played an important role in low bit rate video coding because of its low computation complexity compared to the full search block matching motion estimation algorithm (FBMA). A modular architecture for the three-step hierarchical search BMA is presented, which features a throughput rate, as high as 1/N block per clock cycle, and a low memory bandwidth with random access on-chip local memory. Furthermore, 100% processor utilization has been achieved by using a method called pipeline interleaving. As such, this architecture offers a feasible solution for the Grand Alliance HDTV picture format with a large search range