Title :
Built-in self-test with weighted random pattern hardware
Author :
Brglez, Franc ; Gloster, Clay ; Kedem, Gershon
Author_Institution :
Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
Abstract :
The authors address scan-based built-in self-test (BIST) of digital circuits that are highly resistant to testing with uniform random patterns. Introducing a procedure, the precompute test patterns for random-pattern resistant faults and generate optimized distributions of weights that guarantee pattern coverage in a given number of random trials. The software implementation offers a tradeoff in the number of distributions (hardware memory) and the length of the total test time. The hardware implementation is based on a canonic weighting circuit that interfaces to a circulating memory and a pseudo-random source
Keywords :
built-in self test; digital integrated circuits; integrated circuit testing; logic testing; BIST; canonic weighting circuit; circulating memory; digital circuits; precompute test patterns; pseudo-random source; random-pattern resistant faults; scan-based built-in self-test; uniform random patterns; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Costs; Hardware; Partitioning algorithms; Test pattern generators;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130190
