Title :
An Area-Throughput Efficient FPGA Implementation of the Block Cipher AES Algorithm
Author :
Jyrwa, Banraplang ; Paily, Roy
Author_Institution :
ECE, Dept., NIT Jalandhar, Jalandhar, India
Abstract :
This paper addresses design, hardware implementation and performance testing of AES algorithm. An optimized code for the Rijndael algorithm with 128-bit keys has been developed. The area and throughput are carefully trading off to make it suitable for wireless military communication and mobile telephony where emphasis is on the speed as well as on area of implementation.
Keywords :
cryptography; field programmable gate arrays; military communication; mobile communication; radio access networks; telecommunication security; AES algorithm performance testing; Rijndael algorithm; advanced encryption standard; block cipher AES algorithm; mobile telephony; wireless military communication; word length 128 bit; Algorithm design and analysis; Computer architecture; Cryptography; Field programmable gate arrays; Galois fields; Hardware; Polynomials; Testing; Throughput; Very large scale integration; Advanced Encryption Standard (AES); Cryptography; Encryption; Rijndael; pipelining; security;
Conference_Titel :
Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT '09. International Conference on
Conference_Location :
Trivandrum, Kerala
Print_ISBN :
978-1-4244-5321-4
Electronic_ISBN :
978-0-7695-3915-7
DOI :
10.1109/ACT.2009.88
