A very low-noise low-power integrator for high-resolution ΔΣ modulators

In this paper a very low-noise low-power correlated double sampled integrator has been presented. For attenuating the sampling thermal noise, two large capacitors are incorporated in the integrator without using the large sampling and integrating capacitors that are necessary in ordinary integrators. The integrator is used in the front-end of a 24 bit, fourth-order single-loop single-bit delta-sigma modulator with a bandwidth of 1000 rad/s. A fully differential class AB op-amp with a preamplifier is designed with gain of 85 dB, bandwidth of 12 Mrad/s and overall input referred noise floor of -171 dB without the need for large compensation capacitors as in the ordinary topologies are used. The integrator power consumption is only 2.8 mW with a single 3.0 V supply in 0.6-μm CMOS technology.