A unified delay model for CMOS logic styles

This paper presents a unified model for delay estimation in various CMOS logic styles including conventional, DCVSL, and PTL. It also introduces a simple expression for MOSFET saturation current and derives closed-form optimal transistor sizing formulas for minimizing the delay in each logic style. The paper demonstrates the use of these formulas for delay optimization in mixed logic-style CMOS circuits and reports the results. Mixing CMOS logic styles in a circuit has the potential of improving performance and reducing energy dissipation and area by taking advantage of the strong points in each logic style.