A reconfigurable low IF-zero IF receiver architecture for multi-standard wide area wireless networks

The proliferation of a large number of wireless standards motivates the investigation of a multi-standard wireless receiver architecture that uses the same hardware in meeting widely varying performance requirements. In this paper we develop an innovative low IF- zero IF reconfigurable architecture capable of realizing a single chip CMOS receiver for GSM, PCS 1900 and WCDMA wireless standards. System level analysis and derivation of block level specifications arc done for the multiple standards under consideration. Possible circuit implementations for the RF and analog baseband blocks are presented.