A reconfigurable low IF-zero IF receiver architecture for multi-standard wide area wireless networks

Author

Savla, Anup ; Ravindran, Arun ; Ismail, Mohammed

Author_Institution

Analog VLSI Lab., Ohio State Univ., Columbus, OH, USA

Volume

2

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

934

Abstract

The proliferation of a large number of wireless standards motivates the investigation of a multi-standard wireless receiver architecture that uses the same hardware in meeting widely varying performance requirements. In this paper we develop an innovative low IF- zero IF reconfigurable architecture capable of realizing a single chip CMOS receiver for GSM, PCS 1900 and WCDMA wireless standards. System level analysis and derivation of block level specifications arc done for the multiple standards under consideration. Possible circuit implementations for the RF and analog baseband blocks are presented.

Keywords

CMOS analogue integrated circuits; cellular radio; code division multiple access; phase locked loops; radio access networks; radio receivers; GSM; PCS 1900; RF band select filters; WCDMA; analog baseband blocks; block level specifications; fractional PLL; frequency synthesizer; link budget analysis; low noise amplifier; multistandard wide area wireless networks; reconfigurable low IF-zero IF receiver; single chip CMOS receiver; varying performance requirements; Baseband; Circuits; GSM; Hardware; Multiaccess communication; Personal communication networks; Radio frequency; Reconfigurable architectures; Standards development; Wireless networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301941

Filename

1301941