Title :
68040 memory modules and bus controller
Author :
Martin, Brad ; McMahan, Steve ; Sood, Lal
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
The 68040 processor includes an instruction memory system, a data memory system, and a synchronous bus. These resources are controlled by three autonomous machines, the instruction memory controller (IMEMC), the data memory controller (DMEMC), and the bus controller (BC). The structure of the data paths, the main caches, the address-translation caches, and the controllers are presented, including a discussion of the methodologies used in the development
Keywords :
computer interfaces; microprocessor chips; storage management chips; 68040 processor; IMEMC; Motorola 68000 family; address-translation caches; bus controller; data memory controller; data memory system; data paths; instruction memory controller; main caches; synchronous bus; Counting circuits; Impedance; Memory management; Microprocessors; Operating systems; Pins; Registers; Resistors; Sampling methods; Transmission lines;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130196
