A current mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders

Author

Hemati, Saied ; Banihashemi, Amir H.

Author_Institution

Dept. of Syst. & Comput. Eng., Carleton Univ., Ottawa, Ont., Canada

Volume

1

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

4

Abstract

A new current-mode maximum winner-take-all (max WTA) circuit is presented. Inputs and output of the circuit are high swing, and voltage requirements for the inputs and the output are very low and just about V_eff (V_sat) and 2 V_eff (2 V_sat), respectively. Because of the cascode configuration, the proposed circuit shows very good precision even for short channel MOSFETs. Simulation results based on 0.13 μm UMC CMOS technology are also presented. These results demonstrate the high-precision and low-voltage requirement of the circuit, which makes it a good choice for low-voltage min-sum analog iterative decoders and other soft computing applications.

Keywords

CMOS analogue integrated circuits; current-mode circuits; iterative decoding; low-power electronics; 0.13 micron; 2 V; CMOS technology; cascode configuration; current mode maximum winner-take-all circuit; high-precision decoders; low voltage iterative decoding; max WTA circuit; min-sum analog iterative decoders; short channel MOSFETs; soft computing applications; Broadband communication; CMOS technology; Circuits; Degradation; Iterative decoding; Low voltage; MOSFETs; Parity check codes; Systems engineering and theory; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301962

Filename

1301962