A new time-position algorithm for the modeling of multilevel carry skip adders in VHDL

It must be noted that, though the concept of carry skip has been around for nearly two decades, interest has been shown only recently to optimize and speed-up the design. This is perhaps indicative of the uniform and efficient VLSI design of the adder. Various approaches, both technology dependent and independent, have been dealt with to optimize the design. Our work improves upon some of the algorithms and results in higher bits per group than reported earlier. These results have been further validated by making models of the adder and simulating them in VHDL. The advantages of using VHDL is the quick time-substitution capability the language has to offer