DocumentCode
303017
Title
VLSI implementation of a neural network classifier
Author
Mandisodza, Robson L K ; Luke, David M. ; Pochec, Przemyslaw
Author_Institution
Fac. of Comput. Sci., New Brunswick Univ., Fredericton, NB, Canada
Volume
1
fYear
1996
fDate
26-29 May 1996
Firstpage
178
Abstract
Design and implementation of a neural network classifier is discussed. The classifier is based on the 25 node Hopfield network design. The proposed implementation is on a Xilinx(R) XC4000 FPGA family chip. The design methodology and the resource usage are discussed. An example application of the classifier in pattern recognition is presented
Keywords
Hopfield neural nets; VLSI; circuit CAD; field programmable gate arrays; integrated circuit design; logic CAD; neural chips; pattern recognition; Hopfield network design; VLSI implementation; Xilinx XC4000 FPGA family chip; design methodology; neural network classifier; pattern recognition application; resource usage; Analytical models; Electronic design automation and methodology; Field programmable gate arrays; Hardware design languages; Logic design; Logic devices; Network synthesis; Neural networks; Programmable logic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 1996. Canadian Conference on
Conference_Location
Calgary, Alta.
ISSN
0840-7789
Print_ISBN
0-7803-3143-5
Type
conf
DOI
10.1109/CCECE.1996.548066
Filename
548066
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