Crosstalk noise and delay analysis for high speed on-chip global RLC VLSI interconnects with mutual inductance using 90nm process technology

With continuous scaling of VLSI technology, coupling capacitance between interconnects lines need more accurate transmission line modelling, requiring the introduction of self and mutual inductances. Self and mutual inductances can cause for crosstalk noise and delay between high speeds VLSI interconnects. This paper presents an mathematical computation of crosstalk noise of `L´ Type RLC global interconnects in the presence of self and mutual inductances. This crosstalk noise analysis is carried out for the case when two L type RLC networks are parallel to each other but are not connected, and Step input is applied to the aggressor line which is adjacent to the victim line. This paper also presents to analyze L type interconnect models in deriving mathematical expressions for Peak noise voltage and Delay between adjacent RLC networks with mutual inductance.