Design techniques for soft-error mitigation

In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft-errors, a concern in the past for space applications, became a reliability issue at ground-level. Alpha particles and atmospheric neutrons induce single event upsets (SEU) affecting memory cells, latches and flip-flops, and single event transients (SET) initiated in the combinational logic and captured by the associated latches and flip-flops. To face this challenge, a designer must dispose a variety of soft-error mitigation schemes adapted to various circuit structures, design architectures and design constraints. In this paper, we describe several SEU and SET mitigation schemes that could help designers to meet their reliability constraints.